module lab3(A16,AS,UDS,LDS,osc,clkout,FMEMUCS,FMEMLCS);

input  A16,AS,UDS,LDS,osc;
output FMEMUCS,FMEMLCS,clkout;
wire   FMEMUCS,FMEMLCS,A16,AS,UDS,LDS;

reg clkout;
reg [0:2] count;

assign FMEMUCS=UDS | A16;    //FlashMemory upper (even)
assign FMEMLCS=LDS | A16;    //FlashMemory lower (odd)

always @(posedge osc)
begin
		if(count==5)
		begin 
			count <= 3'b000;
			clkout <= 1'b0;
		end
		else if (count >= 3) 
		begin
			count <= count + 3'b001;
			clkout <= 1'b0;
		end
		else
		begin
			count <= count + 3'b001;
			clkout <= 1'b1;
		end
end

endmodule


